1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory including a sense amplifier for reading out binary information stored in a memory cell in the form of a conductive/non-conductive condition.
2. Description of Related Art
In most of semiconductor memories so configured as to read out information stored in a memory cell which is connected between a digit line and a reference voltage point and which is adapted to store binary information in the form of whether an electric condition between the digit line and the reference voltage point is conductive or non-conductive, a sense amplifier for amplifying a signal corresponding to information stored in the memory cell is of a current detection type
Referring to FIG. 1, there is shown one example of this type conventional semiconductor memory incorporating therein the current detection type sense amplifier.
The shown semiconductor memory comprises a memory cell array 10 including a plurality of digit lines DL1, DL2, . . . , a plurality of word lines WL1, WL2, . . . isolated from the plurality of digit lines and intersecting the plurality of digit lines, a plurality of memory cells MC11, MC12, . . . , MC21, MC22, . . . , . . . respectively located at intersections between the digit lines DL1, DL2, . . . and the word lines WL1, WL2, . . . . Each of the memory cells is connected at its one end to a corresponding digit line and at its other end to ground, and constructed to store binary information in such a manner that when a corresponding word line (gate) is at a selection level, if a diffusion layer has been formed between the one end and the other end of the memory cell, the memory cell is conductive, and if a diffusion layer has not been formed between the one end and the other end of the memory cell, the memory cell is non-conductive.
The semiconductor memory also includes a column selection circuit 20 having N-channel field effect transistors Tr11, Tr22, . . . each having a source connected to a corresponding digit line DL1, DL2, . . . and a drain connected in common to a common node N1. A gate of each of the transistors Tr11, Tr22, . . . is connected to receive a corresponding selection signal Y1, Y2, . . . , so that one digit line is selected from the plurality of digit lines DL1, DL2, . . . by one transistor Tr11, Tr22, or . . . receiving an active selection signal Y1, Y2, or . . . .
Furthermore, the semiconductor memory includes a sense amplifier 30, which comprises a first field effect transistor Tr31 of a P-channel type having a source connected to a voltage supply voltage VDD and a drain connected to the common node N1 A gate of the transistor Tr31 is connected to receive a precharge signal P, so that the transistor Tr31 operates to precharge the common node N1, hence, a digit line selected by the column selection circuit 20, to a predetermined potential at a predetermined timing in response to the precharge signal P. The sense amplifier 30 also comprises an inverting amplifier IV31 having an input connected to receive a signal on the common node N1 (connected to selected digit line) and outputting an inverted signal of the received signal, and a second field effect transistor Tr32x of the P-channel type having a source connected to the voltage supply voltage VDD, a gate connected to an output (node N2) of the inverting amplifier IV31 and a drain connected to the input of the inverting amplifier IV31. This second transistor Tr32x cooperates with the inverting amplifier IV31 so as to maintain a signal level on each of the input and the output of the inverting amplifier IV31. The sense amplifier 30 furthermore comprises an inverting amplifier IV32 receiving an output signal from the inverting amplifier IV31 for outputting an inverted output signal OUT.
Now, operation of the above mentioned semiconductor memory will be described with reference to FIG. 2.
First, explanation will be made on the case of reading out information stored in the memory cell MC12 in which a diffusion layer is not formed.
The precharge signal P is brought from a high level to a low level, and the column selection signal Y1 is brought from a low level to a high level (selection level). At this time, the column selection signal Y2 and the word lines WL1, WL2, . . . are maintained at a low level (non-selection level). Therefore, the transistors Tr31 and Tr21 are turned on, so that the input (node N1) of the inverting amplifier IV31 is brought to a voltage supply voltage level VDD, and the digit line DL1 is precharged to a level of {the voltage supply voltage level VDD minus a threshold of Tr21}.
Thereafter, the precharge signal P is brought to the high level so as to stop the precharging, and on the other hand, the word line WL2 is brought to a high level (selection level), so that the memory cells MC12, MC22, . . . connected to the word line WL2 are put into a selected condition. At this time, depending upon a content (conductive condition or non-conductive condition) stored in each of the memory cells MC12, MC22, . . . , the level of each of the digit lines DL1, DL2, . . . either assumes a ground potential level (in the case of the conductive condition) or remains at the same level as that in a just preceding condition (in the case of the non-conductive condition).
In this example, since the digit line DL1 is selected by the column selection circuit 20, a content stored in the memory cell MC12 selected by the digit line DL1 and the word line WL2 is transmitted to the inverting amplifier IN31. Since no diffusion layer is formed in the memory cell MC12 as mentioned above, the condition between the digit line DL1 and the ground is non-conductive. Accordingly, the digit line DL1 and the node N1 are maintained at the precharge potential (a high level substantially corresponding to the voltage supply voltage level VDD), and the output signal OUT of the voltage supply voltage level VDD (high level) is outputted through the inverting amplifiers IV31 and IV32.
At this time, if a leak current flows out of the digit line DL1, the level of the digit line DL1 is inclined to gradually lower from the precharged level. However, since the transistor Tr32x receiving at its gate the low level output of the inverting amplifier IV31 is turned on so as to maintain the node N1 at the voltage supply voltage level VDD. Namely, the transistor Tr32x functions to compensate for the leak current.
Next, explanation will be made on the case of reading information stored in the memory cell MC22 in which a diffusion layer has been formed.
The precharge signal P is brought to the low level, and the column selection signal Y2 is brought from the high level (selection level). The node N1 and the digit line DL2 are precharged to the voltage supply voltage level VDD and a level of {the voltage supply voltage level VDD minus a threshold of Tr22}, respectively.
Thereafter, the precharge signal P is brought to the high level so as to stop the precharging, and on the other hand, the word line WL2 is brought to a high level (selection level). Since the diffusion layer is formed in the selected memory cell MC22, the condition between the digit line DL2 and the ground is conductive. Accordingly, the digit line DL2 is discharged to the ground potential level, and therefore, the node N1 and hence the output signal OUT are brought to a low level (ground level).
As would be understood from the above, it is sufficient if the transistor Tr32x has an extremely small current driving capability at such a degree as to be able to compensate for the leak current from the digit line connected to the selected memory cell which is in a non-conductive condition (in which no diffusion layer is formed). On the other hand, when the memory cell in the conductive condition (in which the diffusion layer is formed) is selected, it is necessary to make the node N1 and the corresponding digit line as close to the ground potential as possible. Namely, the transistor Tr32x is required to have a sufficiently large on-resistance. Thus, the transistor Tr32x has been designed to have a small channel width and a long channel length so as to have a small current driving capability and a large on-resistance.
In the above mentioned conventional semiconductor memory, since the transistor Tr32x has been designed to have a small channel width and a long channel length, a gate capacitance of the transistor Tr32x is large, and therefore, the inverting amplifier IV31 having the output connected to the gate of the transistor Tr32x becomes to have a large load capacitance. As a result, the read-out operation takes a substantial time.